1. Field of the Invention
The present invention relates to technology that controls the internal impedances of interface buffers in a semiconductor device and to programmable impedance technology, and in particular to technology effectively applied to programmable impedance technology that adapts data output buffers in a semiconductor device such as a SRAM (Static Random Access Memory) to the impedances of transmission lines.
2. Description of the Related Art
When the transmission and reception of data between a semiconductor device and the outside are conducted at a high speed, there are instances where reflectance of the data signals occurs due to the resistance of wiring connected to the outside and a certain constant impedance resulting from inductance and parasitic capacitance, so that normal transmission and reception of the data cannot be conducted. In order to eliminate this data reflectance, the impedances in the semiconductor device and the outside may be matched. However, in principle, semiconductor devices have the characteristic that the internal impedances change easily due to external factors such as the operating voltage and temperature. Thus, dynamic control is conducted so that, after the impedances of output buffers are initially matched to an external impedance for reference (ordinarily, a resistance value that a user has set), the impedances inside the semiconductor device are automatically matched to the outside impedance regardless of the operating voltage and temperature changes.
JP-A-2003-198357 discloses technology that enables dynamic control of the internal impedances even when a read operation continues, so that the precision of the matching of the impedances resulting from a programmable impedance circuit is improved. In other words, in push-pull format output buffers, impedance control data of output transistors placed in an OFF state at the time of an output operation are updated, whereby the output operation is not affected even if the impedances are updated during the output operation.
The present inventor investigated a comparison operation for matching the internal impedances with the programmable impedance circuit. According to this investigation, in the push-pull format output buffers, when attempting to control the output impedances by selecting a number of transistors used in the output operation from numerous output transistors connected in parallel to an output terminal, the transistors used in the output operation are selected by the values of plural bit impedance codes. In order to determine the plural bit impedance codes, a case where the comparison is conducted with a method such as a binary search and comparison operation, where a comparison with the external impedance is conducted from large impedance steps that have been weighted, and a case where the comparison is conducted with a method such as a sequential comparison operation, where a comparison with the external impedance is conducted with impedance steps that have not been weighted, are conceivable.
However, among internal impedance matching operations, there are an initial matching resulting from turning the power ON and an updating operation in an active state thereafter. When both are conducted with the binary search and comparison operation, the initial matching can be conducted quickly, but in the updating operation, there are instances where, even if one impedance control step is changed, that becomes a step with a large impedance. Thus, there is the potential for a large current to flow in the programmable impedance circuit and for the large current to become power supply noise, causing the performance of other circuits to deteriorate. With respect thereto, in the sequential comparison operation, even if one impedance control step is changed, this corresponds only to an LSB 1 bit portion of the impedance codes (it only becomes a small impedance control step that is not weighted), and a large change in the impedance does not occur. However, an enormous amount of time is required for the initial matching. When impedance control is conducted with steps weighted by the power of 2, comparison operations of a maximum of n times may be conducted in the binary search and comparison operation, but when this is conducted with the sequential comparison operation, comparison operations of n-to-the-power-of-2 times must be conducted.